Granted Patent
Utility
US 6,502,222 · App. 09/875,314
Method of clock buffer partitioning to minimize clock skew for an integrated circuit design
Inventor:
Alexander Tetelbaum
Patented Case
View Patent ↗
Granted: Dec 31, 2002
Filed: Jun 4, 2001
Inventor
Alexander Tetelbaum
Assignee (at issue)
LSI Logic Corporation
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.