Granted Patent
Utility
US 6,507,885 · App. 09/496,759
Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure
Inventors:
Vinod Lakhani, Christophe J. Chevallier, Mathew L. Adsitt
Patented Case
View Patent ↗
Granted: Jan 14, 2003
Filed: Feb 3, 2000
Inventors
Vinod Lakhani
Christophe J. Chevallier
Mathew L. Adsitt
Assignee (at issue)
Micron Technology, Inc.
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.