Granted Patent
Utility
US 6,535,959 · App. 09/654,811
Circuit and method for reducing power consumption in an instruction cache
Inventors:
Sumant Ramprasad, Sameer Bidichandani
Patented Case
View Patent ↗
Granted: Mar 18, 2003
Filed: Sep 5, 2000
Inventors
Sumant Ramprasad
Sameer Bidichandani
Assignee (at issue)
Conexant Systems, LLC
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.