IP Library › Granted Patent US 6,548,383
Granted Patent Utility
US 6,548,383 · App. 09/441,912

Twin well methods of forming CMOS integrated circuitry

Inventors: Jigish Trivedi, Zhongze Wang, Michael P. Violette
Patented Case View Patent ↗
Granted: Apr 15, 2003 Filed: Nov 17, 1999
Inventors
Jigish Trivedi
Zhongze Wang
Michael P. Violette
Assignee (at issue)
Micron Technology, Inc.

This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.

Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 6,548,383
App. No.
09/441,912
Filed
1999-11-17
Granted
2003-04-15
Kind
B1