Granted Patent
Utility
US 6,548,896 · App. 10/150,868
Method of reducing shear stresses on IC chips and structure formed thereby
Inventor:
Renato Guida
Patented Case
View Patent ↗
Granted: Apr 15, 2003
Filed: May 20, 2002
Inventor
Renato Guida
Assignee (at issue)
General Electric Company
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.