Granted Patent
Utility
US 6,552,392 · App. 09/899,332
MOS integrated circuit with reduced ON resistance
Inventor:
James D. Beasom
Patented Case
View Patent ↗
Granted: Apr 22, 2003
Filed: Jul 3, 2001
Inventor
James D. Beasom
Assignee (at issue)
Intersil Americas LLC
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.