Granted Patent
Utility
US 6,562,695 · App. 09/889,018
Semiconductor integrated circuit device and method of manufacturing involving the scale-down width of shallow groove isolation using round processing
Inventors:
Norio Suzuki, Hiroyuki Ichizoe, Masayuki Kojima, Keiji Okamoto, Shinichi Horibe, Kozo Watanabe, Yasuko Yoshida, Shuji Ikeda, Akira Takamatsu, Norio Ishitsuka, Atsushi Ogishima, Maki Shimoda
Patented Case
View Patent ↗
Granted: May 13, 2003
Filed: Jul 10, 2001
Inventors
Norio Suzuki
Hiroyuki Ichizoe
Masayuki Kojima
Keiji Okamoto
Shinichi Horibe
Kozo Watanabe
Yasuko Yoshida
Shuji Ikeda
Akira Takamatsu
Norio Ishitsuka
Atsushi Ogishima
Maki Shimoda
Assignees (at issue)
HITACHI, LTD.
Hitachi Ulsi Systems Co., Ltd.
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.