Granted Patent
Utility
US 6,566,239 · App. 09/867,545
Semiconductor device manufacturing method having a step of forming a post terminal on a wiring by electroless plating
Inventors:
Yutaka Makino, Eiji Watanabe, Hirohisa Matsuki, Tetsuya Fujisawa
Patented Case
View Patent ↗
Granted: May 20, 2003
Filed: May 31, 2001
Inventors
Yutaka Makino
Eiji Watanabe
Hirohisa Matsuki
Tetsuya Fujisawa
Assignee (at issue)
Fujitsu Limited
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.