Granted Patent
Utility
US 6,567,287 · App. 09/896,814
Memory device with row and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays
Inventor:
Roy E. Scheuerlein
Patented Case
View Patent ↗
Granted: May 20, 2003
Filed: Jun 29, 2001
Inventor
Roy E. Scheuerlein
Assignee (at issue)
MATRIX SEMICONDUCTOR, INC.
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.