Granted Patent
Utility
US 6,569,739 · App. 10/216,425
Method of reducing the effect of implantation damage to shallow trench isolation regions during the formation of variable thickness gate layers
Inventors:
Arvind Kamath, Venkatesh P. Gopinath
Patented Case
View Patent ↗
Granted: May 27, 2003
Filed: Aug 8, 2002
Inventors
Arvind Kamath
Venkatesh P. Gopinath
Assignee (at issue)
LSI Logic Corporation
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.