IP Library Granted Patent US 6,569,739
Granted Patent Utility
US 6,569,739 · App. 10/216,425

Method of reducing the effect of implantation damage to shallow trench isolation regions during the formation of variable thickness gate layers

Inventors: Arvind Kamath, Venkatesh P. Gopinath
Patented Case View Patent ↗
Granted: May 27, 2003 Filed: Aug 8, 2002
Inventors
Arvind Kamath
Venkatesh P. Gopinath
Assignee (at issue)
LSI Logic Corporation

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Quick Facts
Patent No.
US 6,569,739
App. No.
10/216,425
Filed
2002-08-08
Granted
2003-05-27
Kind
B1