Granted Patent
Utility
US 6,571,365 · App. 09/432,969
Initial stage of a multi-stage algorithmic pattern generator for testing IC chips
Inventors:
James V. Rhodes, Robert David Conklin
Patented Case
View Patent ↗
Granted: May 27, 2003
Filed: Nov 3, 1999
Inventors
James V. Rhodes
Robert David Conklin
Assignee (at issue)
Unisys Corporation
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.