Granted Patent
Utility
US 6,580,176 · App. 09/760,640
Multilayer wiring structure of semiconductor device, method of producing said multilayer wiring structure and semiconductor device to be used for reliability evaluation
Inventors:
Shinichi Domae, Hiroshi Masuda, Yoshiaki Kato, Kousaku Yano
Patented Case
View Patent ↗
Granted: Jun 17, 2003
Filed: Jan 17, 2001
Inventors
Shinichi Domae
Hiroshi Masuda
Yoshiaki Kato
Kousaku Yano
Assignee (at issue)
SUMITOMO ELECTRIC INDUSTRIES, LTD.
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.