Granted Patent
Utility
US 6,587,580 · App. 09/306,590
Stencil printing process optimization for circuit pack assembly using neural network modeling
Inventor:
Khalil N. Nikmanesh
Patented Case
View Patent ↗
Granted: Jul 1, 2003
Filed: May 6, 1999
Inventor
Khalil N. Nikmanesh
Assignee (at issue)
Avaya Technology LLC
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.