Granted Patent
Utility
US 6,593,535 · App. 09/892,045
Direct inner layer interconnect for a high speed printed circuit board
Inventor:
Mark W. Gailus
Patented Case
View Patent ↗
Granted: Jul 15, 2003
Filed: Jun 26, 2001
Inventor
Mark W. Gailus
Assignee (at issue)
Teradyne, Inc.
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.