Granted Patent
Utility
US 6,596,563 · App. 10/091,620
Method for double-layer implementation of metal options in an integrated chip for efficient silicon debug
Inventors:
Xuejun Yuan, Xiaowei Jin, Rambabu Pyapali, Raymond A. Heald, James M. Kaku, Helen Dunn, Thelma C. Taylor, Peter Lai, Aharon Ostrer
Patented Case
View Patent ↗
Granted: Jul 22, 2003
Filed: Mar 4, 2002
Inventors
Xuejun Yuan
Xiaowei Jin
Rambabu Pyapali
Raymond A. Heald
James M. Kaku
Helen Dunn
Thelma C. Taylor
Peter Lai
Aharon Ostrer
Assignee (at issue)
Sun Microsystems Inc.
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.