Granted Patent
Utility
US 6,617,621 · App. 09/588,802
Gate array architecture using elevated metal levels for customization
Inventors:
Tushar R. Gheewala, Duane G. Breid, Deepak D. Sherlekar, Michael J. Colwell
Patented Case
View Patent ↗
Granted: Sep 9, 2003
Filed: Jun 6, 2000
Inventors
Tushar R. Gheewala
Duane G. Breid
Deepak D. Sherlekar
Michael J. Colwell
Assignee (at issue)
Virage Logic Corporation
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.