Granted Patent
Utility
US 6,629,296 · App. 09/627,347
Functional verification of integrated circuit designs
Inventors:
Subbu Ganesan, Shyam Prasad Pillalamarri
Patented Case
View Patent ↗
Granted: Sep 30, 2003
Filed: Jul 28, 2000
Inventors
Subbu Ganesan
Shyam Prasad Pillalamarri
Assignee (at issue)
THARAS SYSTEMS INC.
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.