Granted Patent
Utility
US 6,672,947 · App. 09/924,736
Method for global die thinning and polishing of flip-chip packaged integrated circuits
Inventors:
Chun-Cheng Tsao, John Valliant
Patented Case
View Patent ↗
Granted: Jan 6, 2004
Filed: Aug 7, 2001
Inventors
Chun-Cheng Tsao
John Valliant
Assignee (at issue)
NPTest, Inc.
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.