Granted Patent
Utility
US 6,687,880 · App. 10/245,794
Integrated circuit having a reduced spacing between a bus and adjacent circuitry
Inventors:
Billie J. Rivera, William G. Walker
Patented Case
View Patent ↗
Granted: Feb 3, 2004
Filed: Sep 16, 2002
Inventors
Billie J. Rivera
William G. Walker
Assignee (at issue)
Virtual Silicon Technology, Inc.
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.