Granted Patent
Utility
US 6,697,981 · App. 09/770,186
System and method for evaluating the location of a failure in a logic circuit, and machine-readable recording medium having a recorded program
Inventor:
Kazuki Shigeta
Patented Case
View Patent ↗
Granted: Feb 24, 2004
Filed: Jan 29, 2001
Inventor
Kazuki Shigeta
Assignee (at issue)
NEC CORPORATION
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.