Granted Patent
Utility
US 6,711,092 · App. 10/279,428
Semiconductor memory with multiple timing loops
Inventor:
Deepak Sabharwal
Patented Case
View Patent ↗
Granted: Mar 23, 2004
Filed: Oct 24, 2002
Inventor
Deepak Sabharwal
Assignee (at issue)
Virage Logic Corporation
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.