IP Library › Granted Patent US 6,718,477
Granted Patent Utility
US 6,718,477 · App. 09/519,311

Delay locked loop for an FPGA architecture

Inventors: William C. Plants, Nikhil Mazumder, Arunangshu Kundu, James D. Joseph, Wayne W. Wong
Patented Case View Patent ↗
Granted: Apr 6, 2004 Filed: Mar 6, 2000
Inventors
William C. Plants
Nikhil Mazumder
Arunangshu Kundu
James D. Joseph
Wayne W. Wong

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Quick Facts
Patent No.
US 6,718,477
App. No.
09/519,311
Filed
2000-03-06
Granted
2004-04-06
Kind
B1