Granted Patent
Utility
US 6,728,942 · App. 09/879,142
Method and system for predictive MOSFET layout generation with reduced design cycle
Inventors:
Koen Lampaert, Andy Brotman, Paolo Miliozzi, Paramjit Singh, Mishel Matloubian, Bijan Bhattacharyya
Patented Case
View Patent ↗
Granted: Apr 27, 2004
Filed: Jun 12, 2001
Inventors
Koen Lampaert
Andy Brotman
Paolo Miliozzi
Paramjit Singh
Mishel Matloubian
Bijan Bhattacharyya
Assignee (at issue)
Conexant Systems, LLC
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.