Granted Patent
Utility
US 6,735,683 · App. 10/264,618
Single-chip microcomputer with hierarchical internal bus structure having data and address signal lines coupling CPU with other processing elements
Inventors:
Shumpei Kawasaki, Yasushi Akao, Kouki Noguchi, Atsushi Hasegawa, Hiroshi Ohsuga, Keiichi Kurakazu, Kiyoshi Matsubara, Akio Hayakawa, Yoshitaka Ito
Patented Case
View Patent ↗
Granted: May 11, 2004
Filed: Oct 4, 2002
Inventors
Shumpei Kawasaki
Yasushi Akao
Kouki Noguchi
Atsushi Hasegawa
Hiroshi Ohsuga
Keiichi Kurakazu
Kiyoshi Matsubara
Akio Hayakawa
Yoshitaka Ito
Assignees (at issue)
HITACHI, LTD.
Hitachi VLSI Engineering Corp.
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.