Granted Patent
Utility
US 6,745,160 · App. 09/414,815
Verification of scheduling in the presence of loops using uninterpreted symbolic simulation
Inventors:
Pranav Ashar, Anand Raghunathan, Subhrajit Bhattacharya, Aarti Gupta
Patented Case
View Patent ↗
Granted: Jun 1, 2004
Filed: Oct 8, 1999
Inventors
Pranav Ashar
Anand Raghunathan
Subhrajit Bhattacharya
Aarti Gupta
Assignee (at issue)
NEC CORPORATION
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.