Granted Patent
Utility
US 6,748,352 · App. 09/474,942
Method and apparatus for scan design using a formal verification-based process
Inventors:
Joel T. Yuen, Kailasnath Maneparambil, Puneet Singh
Patented Case
View Patent ↗
Granted: Jun 8, 2004
Filed: Dec 30, 1999
Inventors
Joel T. Yuen
Kailasnath Maneparambil
Puneet Singh
Assignee (at issue)
Intel Corporation
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.