IP Library Granted Patent US 6,774,702
Granted Patent Utility
US 6,774,702 · App. 10/188,685

Fuse trimming failure test circuit for CMOS circuit

Inventor: Ryohei Kimura
Patented Case View Patent ↗
Granted: Aug 10, 2004 Filed: Jul 3, 2002
Inventor
Ryohei Kimura
Assignee (at issue)
SEIKO INSTRUMENTS INC.

This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.

Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 6,774,702
App. No.
10/188,685
Filed
2002-07-03
Granted
2004-08-10
Kind
B2