IP Library › Granted Patent US 6,775,812
Granted Patent Utility
US 6,775,812 · App. 10/197,346

Layout design process and system for providing bypass capacitance and compliant density in an integrated circuit

Inventors: John Andrew Francis Cloudman, Jonathan Lachman, Nicholas Michell
Patented Case View Patent ↗
Granted: Aug 10, 2004 Filed: Jul 17, 2002
Inventors
John Andrew Francis Cloudman
Jonathan Lachman
Nicholas Michell
Assignee (at issue)
Hewlett-Packard Development Company, L.P.

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Quick Facts
Patent No.
US 6,775,812
App. No.
10/197,346
Filed
2002-07-17
Granted
2004-08-10
Kind
B2