Granted Patent
Utility
US 6,777,282 · App. 10/164,626
Method of manufacturing a semiconductor memory device having a memory cell portion including MISFETs with a floating gate and a peripheral circuit portion with MISFETs
Inventors:
Kazuhiro Komori, Toshiaki Nishimoto, Satoshi Meguro, Hitoshi Kume, Yoshiaki Kamigaki
Patented Case
View Patent ↗
Granted: Aug 17, 2004
Filed: Jun 10, 2002
Inventors
Kazuhiro Komori
Toshiaki Nishimoto
Satoshi Meguro
Hitoshi Kume
Yoshiaki Kamigaki
Assignee (at issue)
Renesas Technology Corporation
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.