Granted Patent
Utility
US 6,778,445 · App. 10/353,913
Pipeline nonvolatile memory device with multi-bit parallel read and write suitable for cache memory.
Inventors:
Tsukasa Ooishi, Hiroaki Tanizaki
Patented Case
View Patent ↗
Granted: Aug 17, 2004
Filed: Jan 30, 2003
Inventors
Tsukasa Ooishi
Hiroaki Tanizaki
Assignees (at issue)
Renesas Technology Corporation
MITSUBISHI ELECTRIC ENGINEERING COMPANY, LIMITED
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.