Granted Patent
Utility
US 6,782,521 · App. 10/139,318
Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip
Inventors:
Kevin R. Iadonato, Le Trong Nguyen
Patented Case
View Patent ↗
Granted: Aug 24, 2004
Filed: May 7, 2002
Inventors
Kevin R. Iadonato
Le Trong Nguyen
Assignee (at issue)
SEIKO EPSON CORPORATION
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.