Granted Patent
Utility
US 6,789,169 · App. 09/971,841
Embedded DRAM cache memory and method having reduced latency
Inventor:
Joseph M. Jeddeloh
Patented Case
View Patent ↗
Granted: Sep 7, 2004
Filed: Oct 4, 2001
Inventor
Joseph M. Jeddeloh
Assignee (at issue)
Micron Technology, Inc.
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.