Granted Patent
Utility
US 6,799,310 · App. 10/325,964
Integrated circuit layout method and program for mitigating effect due to voltage drop of power supply wiring
Inventor:
Tetsuo Miyamoto
Patented Case
View Patent ↗
Granted: Sep 28, 2004
Filed: Dec 23, 2002
Inventor
Tetsuo Miyamoto
Assignee (at issue)
Fujitsu Limited
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.