Granted Patent
Utility
US 6,800,898 · App. 09/951,239
Integrated circuit configuration and method of fabricating a dram structure with buried bit lines or trench capacitors
Inventors:
Annalisa Cappelani, Bernhard Sell, Josef Willer
Patented Case
View Patent ↗
Granted: Oct 5, 2004
Filed: Sep 12, 2001
Inventors
Annalisa Cappelani
Bernhard Sell
Josef Willer
Assignee (at issue)
Infineon Technologies AG
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.