Granted Patent
Utility
US 6,809,550 · App. 10/251,402
High speed zero DC power programmable logic device (PLD) architecture
Inventors:
Saroj Pathak, James E. Payne, Victor Nguyen, Harry Kuo
Patented Case
View Patent ↗
Granted: Oct 26, 2004
Filed: Sep 20, 2002
Inventors
Saroj Pathak
James E. Payne
Victor Nguyen
Harry Kuo
Assignee (at issue)
Atmel Corporation
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.