Granted Patent
Utility
US 6,821,808 · App. 10/226,326
CMOS APS with stacked avalanche multiplication layer which provides linear and logarithmic photo-conversion characteristics
Inventors:
Junichi Nakamura, Isao Takayanagi
Patented Case
View Patent ↗
Granted: Nov 23, 2004
Filed: Aug 23, 2002
Inventors
Junichi Nakamura
Isao Takayanagi
Assignee (at issue)
Micron Technology, Inc.
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.