Arithmetic unit for correcting detection output in which corrected operation output is sensitive to mechanical factors
View Patent ↗An arithmetic unit for correcting a detection output of a detector for a mechanical error of the detector in accordance with a predetermined input/output characteristic (straight line) is provided. When a digital output of the detector exceeds an upper limit value stored in a main memory, the digital output becomes a new upper limit value. From a virtual line which passes through the new upper limit value and which is parallel to the straight line, a new lower limit value is obtained. A corrected operation output is obtained in accordance with a new input/output characteristic of the detector based on the new upper limit value and the new lower limit value. Thus, the correction accuracy is improved.
1. An arithmetic unit for allocating a linear analog output obtained from a detector using a predetermined number of discrete levels (2 n ), comprising:
an A/D converter to convert the analog output from the detector into a digital value (Dx);
a memory to store an upper limit value A and a lower limit value B of the digital value (Dx) as predetermined values; and
a controller for perform the following processing steps:
(1) when the digital value (Dx) is A(a 1 ), which exceeds the upper limit value A, updating the upper limit value stored in the memory to A(a 1 );
(2) computing a virtual lower limit value B(a 1 ) from the upper limit value A(a 1 ) in accordance with the slope of a linear function determined by the preset upper limit value A and the preset lower limit value B and updating the lower limit value stored in the memory to the lower limit value B(a 1 ); and
(3) computing an operation output D by calculating the following equation with respect to a subsequently-obtained digital value (Dx):
D =(2 n )×{ Dx−B ( a 1 )}/{ A ( a 1 )− B ( a 1 )}.
2. The arithmetic unit for correcting the detection output according to claim 1 , wherein, every time the digital value (Dx) exceeds the upper limit value A(a 1 ), the processing steps (1), (2), and (3) are performed in accordance with a new upper limit value.
3. The arithmetic unit for correcting the detection output according to claim 1 , wherein, when the digital value (Dx) is B(c 1 ), which falls below the lower limit value B, the following processing steps are performed:
(4) updating the lower limit value stored in the memory to B(c 1 ); and
(5) calculating the following equation using the updated upper limit value and the updated lower limit value:
D =(2 n )×{ Dx−B ( c 1 )}/{ A ( a 1 )− B ( c 1 )}.
4. An arithmetic unit for allocating a linear analog output obtained from a detector using a predetermined number of discrete levels (2 n ), comprising:
an A/D converter to convert the analog output from the detector into a digital value (Dx);
a memory to store an upper limit value A and a lower limit value B of the digital value (Dx) as predetermined values; and
a controller to perform the following processing steps:
(1) when the digital value (Dx) is B(b 1 ), which falls below the lower limit value B, updating the lower limit value stored in the memory to B(b 1 );
(2) computing a virtual upper limit value A(b 1 ) from the lower limit value B(b 1 ) in accordance with a slope of a linear function determined by the preset upper limit value A and the preset lower limit value B and updating the upper limit value stored in the memory to A(b 1 ); and
(3) computing an operation output D by calculating the following equation with respect to a subsequently-obtained digital value (Dx):
D =(2 n )×{ Dx−B ( b 1 )}/{ A ( b 1 )− B ( b 1 )}.
5. The arithmetic unit for correcting the detection output according to claim 4 , wherein, every time the digital value (Dx) falls below the lower limit value B(b 1 ), the processing steps (1), (2), and (3) are performed in accordance with a new lower limit value.
6. The arithmetic unit for correcting the detection output according to claim 4 , wherein, when the digital value (Dx) is A(c 1 ), which exceeds the upper limit value A, the following processing steps are performed:
(4) updating the upper limit value stored in the memory to A(c 1 ); and
(5) calculating the following equation using the updated upper limit value and the updated lower limit value:
D =(2 n )×{ Dx−B ( b 1 )}/{ A ( c 1 )− B ( b 1 )}.
7. The arithmetic unit for correcting the detection output according to claim 1 , wherein, in a case when A 0 represents an actual upper limit value obtained from the A/D converter when an operating range of the detector is at an upper limit and when B 0 represents an actual lower limit value obtained from the A/D converter when the operating range of the detector is at a lower limit, the upper limit value A and the lower limit value B stored in the memory are values taking into consideration a predetermined dead zone α, whereby A=A 0 −α and B=B 0 +α, and
when updating of the the upper limit value and the lower limit value, an updated value is obtained by one of subtracting the dead zone α from the detected value, for the upper limit value, and adding the dead zone α to the detected value, for the lower limit value.
8. The arithmetic unit for correcting the detection output according to claim 4 , wherein, in a case when A 0 represents an actual upper limit value obtained from the A/D converter when an operating range of the detector is at an upper limit and when B 0 represents an actual lower limit value obtained from the A/D converter when the operating range of the detector is at a lower limit, the upper limit value A and the lower limit value B stored in the memory are values taking into consideration a predetermined dead zone α, whereby A=A 0 −α and B=B 0 +α, and
when updating one of the upper limit value and the lower limit value, an updated value is obtained by one of subtracting the dead zone α from the detected value, for the upper limit value, and adding the dead zone α to the detected value, for the lower limit value.