Level-shifter circuit properly operable with low voltage input
A semiconductor integrated circuit includes first and second field-effect transistors which have on/off states thereof being controlled by an incoming signal varying within a first potential range, third and fourth field-effect transistors which are controlled by the on/off states of the first and second filed-effect transistors, a node from which an output signal varying within a second potential range is output according to the on/off states of the first through fourth field-effect transistors, and a control circuit which controls a substrate-bias potential of the first field-effect transistor in response to the incoming signal.
1. A semiconductor integrated circuit, comprising:
first and second field-effect transistors which have on/off states thereof being controlled by an incoming signal varying within a first potential range;
third and fourth field-effect transistors which are controlled by the on/off states of the first and second field-effect transistors;
a node which is a drain of the first field-effect transistor and at which an output signal varying within a second potential range wider than the first potential range is obtained; and
a control circuit which controls a substrate-bias potential of the first field-effect transistor in response to the incoming signal,
wherein gate nodes of the first and second field-effect transistors are not directly connected to gate nodes of the third and fourth field-effect transistors, and
wherein said control circuit is an NMOS transistor that has a first node thereof coupled to the substrate-bias potential of the first field-effect transistor, and has a second node and a gate node thereof coupled to the incoming signal.
2. The semiconductor integrated circuit as claimed in claim 1 , further comprising an NMOS transistor that has a first node thereof coupled to a substrate-bias potential of the second field-effect transistor, and has a second node and a gate node thereof coupled to an inverse of the incoming signal.
3. The semiconductor integrated circuit as claimed in claim 1 , wherein the first and second field-effect transistors are NMOS transistors, and the third and fourth field-effect transistors are PMOS transistors.
4. The semiconductor integrated circuit as claimed in claim 1 , further comprising an inverter which generates an inverse of the incoming signal, wherein the first field-effect transistor is a first NMOS transistor having a gate thereof coupled to the incoming signal and a source thereof coupled to a ground, the second field-effect transistors being a second NMOS transistor having a gate thereof coupled to the output of said inverter and a source thereof coupled to the ground, the third field-effect transistor being a first PMOS transistor having a drain thereof coupled to a drain of the first NMOS transistor, a gate thereof coupled to a drain of the second NMOS transistor, and a source thereof coupled to a power supply potential, and the fourth field-effect transistor being a second PMOS transistor having a drain thereof coupled to the drain of the second NMOS transistor, a gate thereof coupled to the drain of the first NMOS transistor, and a source thereof coupled to the power supply potential.
5. A semiconductor integrated circuit, comprising:
first and second field-effect transistors which have on/off states thereof being controlled by an incoming signal varying within a first potential range;
third and fourth field-effect transistors which are controlled by the on/off states of the first and second field-effect transistors;
a node which is a drain of the first field-effect transistor and at which an output signal varying within a second potential range wider than the first potential range is obtained; and
a control circuit which controls a substrate-bias potential of the first field-effect transistor in response to the incoming signal,
wherein gate nodes of the first and second field-effect transistors are not directly connected to gate nodes of the third and fourth field-effect transistors, and
wherein said control circuit is an NMOS transistor that has a first node thereof coupled to the substrate-bias potential of the first field-effect transistor, and has a second node thereof coupled to an inverse of the incoming signal, with a gate node thereof coupled to the incoming signal.
6. The semiconductor integrated circuit as claimed in claim 5 , further comprising an NMOS transistor that has a first node thereof coupled to a substrate-bias potential of the second field-effect transistor, and has a second node and a gate node thereof coupled to an inverse of the incoming signal.
7. The semiconductor integrated circuit as claimed in claim 5 , wherein the first and second field-effect transistors are NMOS transistors, and the third and fourth field-effect transistors are PMOS transistors.
8. The semiconductor integrated circuit as claimed in claim 5 , further comprising an inverter which generates an inverse of the incoming signal, wherein the first field-effect transistor is a first NMOS transistor having a gate thereof coupled to the incoming signal and a source thereof coupled to a ground, the second field-effect transistors being a second NMOS transistor having a gate thereof coupled to the output of said inverter and a source thereof coupled to the ground, the third field-effect transistor being a first PMOS transistor having a drain thereof coupled to a drain of the first NMOS transistor, a gate thereof coupled to a drain of the second NMOS transistor, and a source thereof coupled to a power supply potential, and the fourth field-effect transistor being a second PMOS transistor having a drain thereof coupled to the drain of the second NMOS transistor, a gate thereof coupled to the drain of the first NMOS transistor, and a source thereof coupled to the power supply potential.
9. A semiconductor integrated circuit, comprising:
first and second field-effect transistors which have on/off states thereof being controlled by an incoming signal varying within a first potential range;
third and fourth field-effect transistors which are controlled by the on/off states of the first and second field-effect transistors;
a node which is a drain of the first field-effect transistor and at which an output signal varying within a second potential range wider than the first potential range is obtained; and
a control circuit which controls a substrate-bias potential of the first field-effect transistor in response to the incoming signal,
wherein gate nodes of the first and second field-effect transistors are not directly connected to gate nodes of the third and fourth field-effect transistors, and
wherein said control circuit is a signal line that provides a direct coupling between the substrate-bias potential of the first field-effect transistor and the incoming signal.
10. A semiconductor integrated circuit, comprising:
first and second field-effect transistors which have on/off states thereof being controlled by an incoming signal varying within a first potential range;
third and fourth field-effect transistors which are controlled by the on/off states of the first and second field-effect transistors;
a node from which an output signal varying within a second potential range is output according to the on/off states of the first through fourth field-effect transistors; and
a control circuit which controls a substrate-bias potential of the first field-effect transistor in response to the incoming signal,
wherein said control circuit is an NMOS transistor that has a first node thereof coupled to the substrate-bias potential of the first field-effect transistor, and has a second node and a gate node thereof coupled to the incoming signal.
11. The semiconductor integrated circuit as claimed in claim 10 , further comprising an NMOS transistor that has a first node thereof coupled to a substrate-bias potential of the second field-effect transistor, and has a second node and a gate node thereof coupled to an inverse of the incoming signal.
12. A semiconductor integrated circuit, comprising:
first and second field-effect transistors which have on/off states thereof being controlled by an incoming signal varying within a first potential range;
third and fourth field-effect transistors which are controlled by the on/off states of the first and second field-effect transistors;
a node from which an output signal varying within a second potential range is output according to the on/off states of the first through fourth field-effect transistors; and
a control circuit which controls a substrate-bias potential of the first field-effect transistor in response to the incoming signal,
wherein said control circuit is an NMOS transistor that has a first node thereof coupled to the substrate-bias potential of the first field-effect transistor, and has a second node thereof coupled to an inverse of the incoming signal, with a gate node thereof coupled to the incoming signal.
13. The semiconductor integrated circuit as claimed in claim 12 , further comprising an NMOS transistor that has a first node thereof coupled to a substrate-bias potential of the second field-effect transistor, and has a second node and a gate node thereof coupled to an inverse of the incoming signal.
14. A semiconductor integrated circuit, comprising:
first and second field-effect transistors which have on/off states thereof being controlled by an incoming signal varying within a first potential range;
third and fourth field-effect transistors which are controlled by the on/off states of the first and second field-effect transistors;
a node from which an output signal varying within a second potential range is output according to the on/off states of the first through fourth field-effect transistors; and
a control circuit which controls a substrate-bias potential of the first field-effect transistor in response to the incoming signal,
wherein said control circuit is a signal line that provides a direct coupling between the substrate-bias potential of the first field-effect transistor and the incoming signal.