SAR with partial capacitor sampling to reduce parasitic capacitance
SAR with partial capacitor sampling to reduce parasitic capacitance. An analog-to-digital convertor is disclosed with reduced parasitic capacitance on the input during a sampling operation. A charge-redistribution, binary-weighted switched-capacitor array is included having a plurality of array capacitors that each have a commonly connected plate interfaced to a first common node and a switched plate, the switched plate operable to be switched between first and second reference voltages during a redistribution phase and select ones of the capacitors additionally operable to be switched to the input during a sampling phase. Each of the array capacitors has a parasitic capacitance associated therewith. A compensation capacitor having a common plate is connected to the first common node and a switched plate, the compensation capacitor operable to be switched to the input during the sampling phase and to the first reference voltage during the redistribution phase. The compensation capacitor has a parasitic capacitance less than the parasitic capacitance of the combination of all of the non select ones of the array capacitors. A comparator compares the voltage on the first common node to a compare reference voltage during the redistribution phase. A successive approximation controller is provided for switching the switched plate of the array capacitors between the first and second reference voltages in accordance with a successive approximation algorithm during the redistribution phase.
1. An analog-to-digital converter with reduced parasitic capacitance on the input during a sampling operation, comprising:
a charge-redistribution, binary-weighted switched-capacitor array having a plurality of array capacitors that each have a commonly connected plate interfaced to a first common node and a switched plate, said switched plate operable to be switched between first and second reference voltages during a redistribution phase and selected ones of said capacitors additionally operable to be switched to the input during a sampling phase;
each of said array capacitors having a parasitic capacitance associated therewith;
a compensation capacitor having a common plate connected to said first common node and a switched plate operable to be switched to the input during the sampling phase and to said first reference voltage during the redistribution phase, the parasitic capacitance thereof less than the parasitic capacitance of the combination of all of said non-selected ones of said array capacitors;
a comparator for comparing the voltage on said first common node to a compare reference voltage during the redistribution phase; and
a successive approximation controller for switching the switched plate of said array capacitors between said first and second reference voltages in accordance with a successive approximation algorithm during the redistribution phase.
2. The analog-to-digital converter of claim 1 , wherein said compensation capacitor has a value that is substantially equal to the value of the equivalent capacitance of all of said non-selected array capacitors connected to said first common node.
3. The analog-to-digital converter of claim 2 , wherein said switched-capacitor array comprises a bridge capacitor array, including:
at least first and second array sections;
said first array section associated with said first common node and said second array section associated with a second common node;
said second common node separated from said first common node by a series capacitor;
said non-selected array capacitors inclusive of said array capacitors in said second section; and
wherein said compensation capacitor has a value equal to the equivalent capacitance loaded on said first common node said from non-selected array capacitors in said second section.
4. The analog-to-digital converter of claim 3 , wherein at least one of said array capacitors in said first section comprises one of said non-selected array capacitors.
5. The analog-to-digital converter of claim 4 , wherein the at least one of said array capacitors in said first section that comprises one of said non-selected array capacitors comprises the smallest capacitance value in said first section.
6. The analog-to-digital converter of claim 3 , wherein said compensation capacitor has a parasitic capacitance proportionally equal to the parasitic capacitance of each of said array capacitors based on the relative values thereof.
7. The analog-to-digital converter of claim 1 , wherein said compare reference voltage comprises a common mode reference voltage.
8. The analog-to-digital converter of claim 7 , wherein said common mode reference voltage is generated by a low impedance common mode driver.
9. The analog-to-digital converter of claim 8 , wherein said low impedance common mode driver is operable to drive said first common node during the sampling phase.
10. The analog-to-digital converter of claim 1 , wherein said successive approximation controller is operable to switch all of the switched plates of said array capacitors and the switched plate of said compensation capacitor to said first reference voltage substantially immediately after the sampling phase during a hold phase, and then selectively switching the switched plates of said array capacitors to said second reference voltage in accordance with the successive approximation algorithm and then testing the output of said comparator.
11. The analog-to-digital converter of claim 10 , wherein said first reference voltage comprises system ground.
12. The analog-to-digital converter of claim 1 , wherein said first reference voltage comprises system ground.
13. A method for converting data with an analog-to-digital converter with reduced parasitic capacitance on the input during a sampling operation, comprising the steps of:
forming a charge-redistribution, binary-weighted switched-capacitor array having a plurality of array capacitors that each have a commonly connected plate interfaced to a first common node and a switched plate, the switched plate operable to be switched between first and second reference voltages during a redistribution phase and selected ones of the capacitors additionally operable to be switched to the input during a sampling phase;
each of the array capacitors having a parasitic capacitance associated therewith;
connecting a common plate of a compensation capacitor to the first common node and switching a switched plate of the compensation capacitor to the input during the sampling phase and to the first reference voltage during the redistribution phase, the parasitic capacitance thereof less than the parasitic capacitance of the combination of all of the non-selected ones of the array capacitors;
comparing with a comparator the voltage on the first common node to a compare reference voltage during the redistribution phase; and
switching with a successive approximation controller the switched plate of the array capacitors between the first and second reference voltages in accordance with a successive approximation algorithm during the redistribution phase.
14. The method of claim 13 , wherein the compensation capacitor has a value that is substantially equal to the value of the equivalent capacitance of all of the non-selected array capacitors connected to the first common node.
15. The method of claim 14 , wherein the switched-capacitor array comprises a bridge capacitor array, including:
at least first and second array sections;
the first array section associated with the first common node and the second array section associated with a second common node;
the second common node separated from the first common node by a series capacitor;
the non-selected array capacitors inclusive of the array capacitors in the second section; and
wherein the compensation capacitor has a value equal to the equivalent capacitance loaded on the first common node the from non-selected array capacitors in the second section.
16. The method of claim 15 , wherein at least one of the array capacitors in the first section comprises one of the non-selected array capacitors.
17. The method of claim 15 , wherein the at least one of the array capacitors in the first section that comprises one of the non-selected array capacitors comprises the smallest capacitance value in the first section.
18. The method of claim 15 , wherein the compensation capacitor has a parasitic capacitance proportionally equal to the parasitic capacitance of each of the array capacitors based on the relative values thereof.
19. The method of claim 13 , wherein the compare reference voltage comprises a common mode reference voltage.
20. The method of claim 19 , further including the step of generating the common mode voltage with a low impedance common mode driver.
21. The method of claim 20 , wherein the step of generating is operable to drive the first common node with the common mode voltage during the sampling phase.
22. The method of claim 13 , wherein the step of switching with the successive approximation controller is operable to switch all of the switched plates of the array capacitors and the switched plate of the compensation capacitor to the first reference voltage substantially immediately after the sampling phase during a hold phase, and then selectively switching the switched plates of the array capacitors to the second reference voltage in accordance with the successive approximation algorithm and then testing the output of the comparator.
23. The method of claim 22 , wherein the first reference voltage comprises system ground.
24. The method of claim 13 , wherein the first reference voltage comprises system ground.