Fully integrated solid state imager and camera display
View Patent ↗There is shown an single chip CMOS device for capturing a video image. The device includes an APS imager containing an array of pixels for providing a signal representing a scene, a row of extended dynamic range sample and hold circuits for receiving a signal from the array of pixels and a row of linear sample and hold circuits for receiving another signal for said array of pixels. Also included is an image processor for determining a controllable function and for processing a plurality of signals received from the extended dynamic range sample and hold circuits and the linear sample and hold circuits according to said controllable function to form a processed video signal. Further included is a memory for storing the controllable function and the processed video signal.
1. A single chip, CMOS imaging device comprising:
an array of pixels for providing a signal representing a scene;
pixel reset circuitry for resetting said pixels in said array of pixels according to a reset sequence, wherein said reset sequence controls both timing and reset potential;
a row of extended dynamic range sample and hold circuits for receiving a signal from said array of pixels;
a row of linear sample and hold circuits for receiving another signal from said array of pixels;
memory control and histogram circuitry which is configured to be used to generate a histogram of said signal from said array of pixels and to determine if said histogram of said signal is within predetermined limits, wherein said reset sequence is configured to be adjusted if said histogram of said signal is not within said predetermined limits;
an image processor for determining a controllable function and for processing a plurality of signals received from said extended dynamic range sample and hold circuits and said linear sample and hold circuits according to said controllable function to form a processed video signal; and
a memory for storing said controllable function and said processed video signal.
2. The device of claim 1 , wherein said memory is dual-ported.
3. The device of claim 1 , wherein said image processor transmits timing and control signals to said array of pixels.
4. The device of claim 1 , further comprising a regulated power supply.
5. The device of claim 4 , further comprising a watchdog circuit for receiving a timing signal from said regulated power supply.
6. The device of claim 5 , wherein an output from said watchdog circuit comprises a trigger pulse for said image processor.
7. The device of claim 1 , further comprising a digital to analog converter coupled to said image processor to convert said processed video signal into a predetermined format.
8. The device of claim 7 , wherein an output from said digital to analog converter is an interlaced video signal.
9. The device of claim 7 , wherein said digital to analog converter outputs an RS-170 compliant video signal.
10. The device of claim 1 , wherein said array of pixels contains an array of photodetectors.
11. The device of claim 1 , wherein said array of pixels is an active pixel sensor device.
12. The device of claim 1 , wherein said image processor is programmable based on at least one of i) a position of the imaging device, ii) a scan path of the imaging device, iii) a time of day and iv) a day of year.
13. A method of processing a signal from an imaging device comprising the steps of:
a) receiving an image representing a scene from an image array;
b) generating a histogram of the image;
c) determining if the image includes a portion having a predetermined brightness and a predetermined dynamic range based on the histogram;
d) determining if a current reset sequence is an initial reset sequence based on the result of step c);
e) determining if the current reset sequence was changed based on the determination of step d) and whether the image received in step a) is an improved image over an immediately previous image; and
f) changing the reset sequence based on the result of step e).
14. A method according to claim 13 further comprising the steps of:
g) determining if the current reset sequence has changed from a last reset sequence based on the result of step c);
h) determining if the current reset sequence was previously changed based on the result of step g);
i) determining whether there is an improvement in the image based on the result of step h); and
j) changing a reset level based on the result of step i).
15. A method according to claim 13 , further comprising the step of simultaneously performing histogramming operations during the reset sequence adjustments.
16. A method according to claim 13 , wherein said determination of step b) is based on a histogram of the image having at least 100 pixels that are within about 10 percent of a maximum brightness level for the image array.
17. A method according to claim 13 , wherein said determination of step e) is based on comparing a highest level of the histogram generated in step b) with a highest level of a histogram for the immediately previous image.