Selective post-doping of gate structures by means of selective oxide growth
View Patent ↗A method for doping a polysilicon gate conductor, without implanting the substrate in a manner that would effect source/drain formation is provided. The inventive method comprises forming at least one polysilicon gate region atop a substrate; forming oxide seed spacers abutting the polysilicon gate; forming source/drain oxide spacers selectively deposited on the oxide seed spacers by liquid phase deposition, and implanting at least one polysilicon gate region, wherein the source/drain oxide spacers protect an underlying portion of the substrate. Multiple gate regions may be processed on a single substrate using conventional patterning. A block-mask provided by patterned photoresist can be used prior to implantation to pre-select the substrate area for gate conductor doping with one dopant type.
1. A method of doping a gate conductor comprising:
forming at least one polysilicon gate atop a substrate;
forming at least one set of spacers abutting said at least one polysilicon gate, said at least one set of spacers having an exterior oxide surface;
forming source/drain oxide spacers by liquid phase deposition, said source/drain oxide spacers being selectively deposited on said exterior oxide surface of said at least one set of spacers, wherein a top surface of said at least one polysilicon gate is exposed; and
implanting said at least one polysilicon gate region, wherein said source/drain oxide spacers protect an underlying portion of said substrate.
2. The method of claim 1 wherein prior to forming said source/drain oxide spacers an exposed surface of said substrate is treated with a chemical clean composition to remove native oxide.
3. The method of claim 1 wherein each spacer of said source/drain oxide spacers has a source/drain oxide spacer width of less than about 150.0 nm.
4. The method of claim 1 wherein said at least one set of spacers comprises oxide, nitride, or oxynitride material.
5. The method of claim 1 wherein forming said at least one set of spacers comprises a deposition process and an etch process.
6. The method of claim 1 wherein said at least one spacer comprises a nitride spacer, wherein said exterior oxide portion is an oxide seed layer positioned on an exterior surface of said nitride spacer.
7. The method of claim 6 wherein said oxide seed layer is SiO 2 .
8. The method of claim 7 wherein said SiO 2 is deposited from a tetraethyl othrosililicate (TEOS) source, which may include the addition of ozone (O 3 ).
9. The method of claim 1 wherein said oxide seed layer is formed by chemical vapor deposition (CVD), plasma-assisted CVD, low-pressure chemical vapor deposition (LPCVD) or thermal oxidation.
10. The method of claim 1 wherein said liquid phase deposition comprises dipping said substrate in a supersaturated hydrofluosilicic acid (H 3 SiF 6 ).
11. The method of claim 10 wherein said supersaturated hydrofluosilicic acid (H 3 SiF 6 ) is produced by adding aqueous boric acid (H 3 BO 3 ) to a saturated hydrofluosilicic acid (H 3 SiF 6 ) until a precipitate is formed, wherein said precipitate is adsorbed by said exterior oxide surface, forming said source/drain oxide spacer.
12. The method of claim 11 wherein said a saturated hydrofluosilicic acid (H 3 SiF 6 ) is produced by adding SiO 2 powder to a hydrofluoric acid base until a solution at maximum equilibrium is provided.
13. The method of claim 12 wherein said supersaturated hydrofluosilicic acid (H 3 SiF 6 ) is produced by adding aluminum to a saturated hydrofluosilicic acid (H 3 SiF 6 ) until a precipitate is formed, wherein said precipitate is adsorbed by said exterior oxide surface forming said source/drain oxide spacer.
14. The method of claim 1 wherein said implanting said at least one polysilicon gate region comprises ion implantation of a n-type or p-type dopant, wherein said p-type dopants are group III elements and said n-type dopants are group V elements.
15. The method of claim 1 further comprising stripping said source/drain oxide spacers.
16. The method of claim 1 wherein said at least one polysilicon gate is implanted with a dose from about 1×10 15 cm −2 to about 5×10 15 cm −2 , using an implant energy ranging from about 4.0 keV to about 30.0 keV.
17. The method of claim 1 wherein said source/drain oxide spacer comprises SiO 2 with a fluorine impurity concentration of less than 5.0 atomic weight %.
18. A method of doping multiple gate regions comprising:
forming a plurality of polysilicon gates on a substrate;
providing doped regions in said substrate;
forming source/drain oxide spacers by liquid phase deposition, said source/drain oxide spacers being selectively deposited on an exterior oxide portion of at least one set of spacers flanking at least one of said plurality of polysilicon gates;
forming a block mask overlying a device region including a portion of said plurality of polysilicon gates, wherein another device region including an exposed portion of said plurality of polysilicon gates is implanted with a first type dopant;
removing said block mask;
applying another block mask overlying previously doped polysilicon gates, wherein another exposed portion of said plurality of polysilicon gates are implanted with a second dopant;
removing said other block mask;
stripping said source/drain oxide spacers;
activating said doped regions and said plurality of polysilicon gates; and
providing interconnectivity to said source/drain region and said plurality of polysilicon gates.
19. The method of claim 18 wherein said at least one set of spacers comprise a first set of spacers and a second set of spacers.
20. The method of claim 19 wherein providing doped regions further comprises
forming said first set of spacers abutting said plurality of gate regions;
implanting first dopant type source/drain extension regions and second dopant type extension regions, wherein said second dopant type source/drain extension regions are selectively implanted in said device region and said first dopant type source/drain extension regions are implanted in said other device region;
forming said second set of spacers abutting said first set of spacers; and
implanting first dopant type source/drain diffusion regions and second dopant type diffusion regions, wherein said second dopant type source/drain diffusion regions are selectively implanted in said device region and said first dopant type source/drain diffusion regions are implanted in said other device region.
21. The method of claim 19 wherein said doped regions are source/drain extension regions.
22. The method of claim 21 wherein said implanting said exposed portion of polysilicon gates with said first type dopant produces first type dopant deep source/drain regions and said implanting said other exposed portion of said plurality of polysilicon gates with a second dopant produces second type deep source/drain regions.
23. The method of claim 22 wherein following forming said second type deep source/drain regions said source/drain oxide spacers are removed from said exposed portion of said plurality of polysilicon gates and first type dopant source/drain diffusion are implanted prior to said removing said block mask.
24. The method of claim 22 wherein following forming said first type deep source/drain said source/drain oxide spacers are removed from said other exposed portion of said plurality of polysilicon gates and second type dopant source/drain diffusion regions are implanted prior to said removing said other block mask.
25. The method of claim 18 wherein said first dopant is an n-type dopant and said second dopant is a p-type dopant, wherein said p-type dopant is a group III element and said n-type dopant is a group V element.
26. The method of claim 18 wherein said liquid phase deposition comprises dipping said substrate in a supersaturated hydrofluosilicic acid (H 3 SiF 6 ).
27. The method of claim 18 wherein said supersaturated hydrofluosilicic acid (H 3 SiF 6 ) is produced by adding aqueous boric acid (H 3 BO 3 ) to a saturated hydrofluosilicic acid (H 3 SiF 6 ) until a precipitate is formed, wherein said precipitate is adsorbed by said oxide offset spacers forming said source/drain oxide spacers.
28. The method of claim 18 wherein said source/drain oxide spacers has a width of less than about 150.0 nm and a composition comprising SiO 2 with a fluorine impurity concentration of less than 5.0 atomic weight %.