Bimetal layer manufacturing method
A bimetal layer manufacturing method includes the procedure of: forming a first dielectric layer on the surface of a semiconductor substrate which has a first metal layer (conductive layer) of a selected pattern formed thereon; forming a SOG layer on the surface of the first dielectric layer; forming a second dielectric layer; forming required via holes on the foregoing layers until reaching the first metal layer; forming a linear layer from a dielectrics material through PECVD; removing unnecessary linear layer from selected locations through an anisotropic plasma etching process; finally forming a second metal layer on a selected surface of the linear layer where MIM capacitors to be formed, and forming connection plugs in the via openings without generating via hole poison.
1. A bimetal layer manufacturing method, comprising:
providing a semiconductor substrate which has a first metal layer of a selected pattern formed thereon and forming a first dielectric layer on the surfaces of the substrate and the first metal layer;
forming a SOG layer on the surface of the first dielectric layer to flatten the surface thereof;
forming a second dielectric layer and forming required via holes on the second dielectric layer, the SOG layer and the first dielectric layer until reaching the first metal layer;
forming a linear layer through plasma enhance chemical vapor deposition (PECVD);
removing selectively the linear layer not required in downstream fabrication processes through an anisotropic plasma etching process, and maintaining the linear layer on a side wall of the via holes; and
forming a second metal layer pattern to obtain a desired MIM capacitor;
wherein the second metal layer forms a connection plug which is prevented from direct contact with the SOG layer by the linear layer on the side wall.
2. The method of claim 1 , wherein the first metal layer and the second metal layer are selected from the group consisting of aluminum, copper, aluminum copper alloy, and aluminum copper and silicon alloy.
3. The method of claim 1 , wherein the first dielectric layer and the second dielectric layer are made from dielectric material of a low dielectric constant that are selected from the group consisting of silicon dioxide, silicon nitride, nitrogen silicon oxide, phosphor silicon glass, and boron phosphor silicon glass.
4. The method of claim 1 , wherein the SOG layer is a nitride SOG layer.
5. The method of claim 1 , wherein the linear layer is made from dielectric material.
6. The method of claim 5 , wherein the dielectric material is selected from the group consisting of titanium nitride, tantalum nitride, and silicon nitride.