IP Library Granted Patent US 7,088,872
Granted Patent B1
US 7,088,872 · App. 10/366,955 · Granted Aug 8, 2006

Method and apparatus for two dimensional image processing

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,088,872
App. No.
10/366,955
Granted
Aug 8, 2006
Kind
B1
Abstract

In one embodiment, the present invention is a system for two dimensional digital image processing. The system includes a memory access module for accessing a memory containing image data to be processed, and a data flow organizer module for preparing a data stream from the input image data accessed by the memory access module. The data flow organizer module predicts future data neede for processing, and the memory access module pre-fetches the predicted data from the memory. A data processing module processes the pre-fetched data from the data flow organizer module. Address generation for accessing the memory is performed independent and in parallel with processing the pre-fetched data.

Claims (72)

1. A system for two dimensional digital data processing comprising:

a memory access module for accessing a memory containing image data to be processed;

a data flow organizer module for preparing input image data accessed by the memory access module, wherein the data flow organizer module predicts future data needed for processing and pre-fetches the predicted data from the memory; and

a data processing module for processing the pre-fetched data from the data flow organizer module, wherein address generation for accessing the memory is performed independent and in parallel with processing the pre-fetched data.

2. The system of claim 1 , further comprising a histogram module coupled between the data flow organizer module and the data processing module for calculating statistic information for the input image data within a specified window.

3. The system of claim 1 , wherein the memory access module comprises at least one read address generation unit for a read operation and at least one write address generation unit for a write operation, and wherein each of the read and write address generation units are designed for block data transfer.

4. The system of claim 3 , wherein each of the read and write address generation units are designed for one or more of line scan and column scan modes.

5. The system of claim 3 , wherein each of the read and write address generation units point to a specific area in the memory.

6. The system of claim 1 , wherein the data flow organizer module comprises:

a cache memory for storing data;

a memory table coupled to the cache memory for storing a plurality of image attributes;

at least two read address generator units for generating data read address;

at least two write address generator units for generating data write address;

a multiplexor coupled to the at least two read address generator units and the at least two write address generator units for multiplexing the data read address and data write address; and

synchronization logic for synchronizing the at least two read address generator units and the at least two write address generator units responsive to the stored plurality of image attributes.

7. The system of claim 6 , wherein the cache memory is a dual-port RAM.

8. The system of claim 6 , wherein the cache memory is a single-port RAM.

9. The system of claim 1 , wherein the data processing module comprises:

a plurality of registers for controlling input data flow and output data flow;

a computation unit coupled to some of the a plurality of registers for performing arithmetic and logic calculations

an instruction/data memory coupled to the computation unit for storing instructions and data;

an execution controller for controling instruction flow and accessing the instruction/data memory; and

a pipeline output interface for controling flow of the output data.

10. The system of claim 2 , wherein the histogram module comprises:

a de-coupler module for receiving a digital encoded signal and outputting two signals;

a pipelined histogram module coupled to the de-coupler module for determining a histogram of an input image;

a LMBD module for obtaining maximum and minimum gray levels in a histogram array;

a statistics calculator for calculating a mean gray value based on the histogram; and

a synchronization control unit controlling synchronization between the de-coupler module, the pipelined histogram module, the LMBD module; and the statistics calculator.

11. A method for two dimensional digital data processing comprising:

predicting future data needed for processing;

generating memory access address for predicted future data;

pre-fetching the predicted data from an image memory responsive to generated memory access address;

processing the pre-fetched data, wherein generating memory access address is performed independent and in parallel with processing the pre-fetched data.

12. The method of claim 11 , further comprising calculating statistic information for an input image data within a specified window by a histogram module.

13. The method of claim 11 , wherein the pre-fetching the predicted data is performed by block data transfer.

14. The method of claim 13 , wherein the pre-fetching the predicted data is performed by one or more of line scan and column scan modes.

15. The method of claim 11 , wherein the predicting future data comprises:

storing data in a cache memory;

storing a plurality of image attributes in a memory table;

generating data read address;

generating data write address; and

synchronizing the generation of data read address and data write address responsive to the stored plurality of image attributes.

16. The method of claim 11 , wherein the processing the pre-fetched data comprises:

controlling input data flow and output data flow by a plurality of registers;

performing arithmetic and logic calculations by a computation unit;

storing instructions and data in an instruction/data memory;

accessing the instruction/data memory;

controling instruction flow by an execution controller; and

controling flow of the output data by a pipeline output interface.

17. The method of claim 12 , wherein the calculating statistic information comprises:

receiving a digital encoded signal and outputting two signals by a de-coupler module;

determining a histogram of an input image by a pipelined histogram module;

obtaining maximum and minimum gray levels in a histogram array;

calculating a mean gray value based on the histogram; and

synchronization the receiving, the determining a histogram, and the obtaining maximum and minimum gray levels steps.

18. A method for two dimensional digital image processing comprising:

predicating needed image data in advance;

generating address for the needed image data by utilizing spatial locality information about an image stored in an image memory;

retrieving the needed image data from the image memory;

storing the image data in a data flow organizing module;

processing the stored image data, wherein address generation for accessing the memory is performed independent and in parallel with processing the pre-fetched data; and

removing the stored image data from the data flow organizing module after the data is used and is no longer needed.

19. The method of claim 18 , further comprising calculating statistic information for an input image data within a specified window by a histogram module.

20. The method of claim 18 , wherein the retrieving the needed image data is performed by block data transfer.

21. The method of claim 18 , wherein the retrieving the needed image data is performed by one or more of line scan and column scan modes.

22. The method of claim 18 , wherein the predicting needed image data step comprises:

storing data in a cache memory;

storing a plurality of image attributes in a memory table;

generating data read address;

generating data write address; and

synchronizing the generation of data read address and data write address responsive to the stored plurality of image attributes.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2023
From: THALES DIS FRANCE SA
To: THALES DIS FRANCE SAS
Reel/Frame 064898/0413 →
CHANGE OF NAME Recorded Sep 11, 2023
From: GEMALTO SA
To: THALES DIS FRANCE SA
Reel/Frame 064855/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 11, 2017
From: 3M COGENT, INC.
To: GEMALTO SA
Reel/Frame 042962/0397 →
MERGER Recorded Jun 2, 2011
From: COGENT SYSTEMS, INC.
To: COGENT, INC.
Reel/Frame 026376/0381 →
MERGER AND NAME CHANGE Recorded Jun 2, 2011
From: COGENT, INC.
To: 3M COGENT, INC.
Reel/Frame 026376/0673 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 6, 2003
From: HSIEH, MING; XUE, HUANSHENG; WANG, JING; LU, CHUNYU
To: COGENT SYSTEMS INC.
Reel/Frame 014153/0288 →