Memory compiler redundancy
View Patent ↗An improved redundancy architecture for embedded memories in an ASIC chip includes one or more compiler-generated embedded memory instances. Each embedded memory instance has a universal register for storing an address of a defective subunit of the memory instance from a variety of sources. A control block is located on the ASIC chip outside of the memory instances. The control block has a defective memory register for storing an address of a defective memory subunit. The address of a defective memory subunit from the defective memory register in the control block is transferred to the universal interface register in the memory instance. In one embodiment, the control block includes fuses for storing a defective subunit address in binary form. A fuse array is located outside of the memory instances and contains laser fuses that represent address of defective subunits for each memory instance. Alternatively, the control block includes a BISTDR (built-in, self-test, diagnostic, and repair) system that provides an address of a defective memory subunit. Means are provided in the memory instances for comparing incoming memory addresses to address bits for defective memory subunits stored in each memory-instance register.
1. An integrated circuit that is created by a memory compiler, comprising:
an ASIC having one or more compiler-generated embedded memory instances of an ASIC compiler, each of said memory instances having a memory array and having a universal interface register for storing an address of a defective subunit of said memory array;
a fuse array that is located outside of the memory instances and that contains laser fuses that represents addresses of defective subunits for each memory instance;
said fuse array control block having a plurality of registers for storing the address of defective subunits for each memory instance;
means for transferring the address of one or more defective subunits for each memory instance to a corresponding memory instance; and
means for comparing incoming memory addresses to address bits for defective memory subunits stored in each memory-instance register.
2. An apparatus comprising:
an integrated circuit chip (IC) including a memory array and compiler-generated embedded memory instances of a IC compiler, a memory instance including a universal interface register for storing a memory address of a defective subunit of said memory array;
a fuse array located outside of the memory instances and including laser fuses to represent a memory addresses of defective subunits and a fuse array control block including registers for storing memory addresses of a defective subunits; and
a comparator to compare incoming memory addresses to address bits for the defective memory subunits stored in the universal registers.
3. The apparatus of claim 2 , wherein the addresses of defective memory units are stored in the universal interface register.