IP Library Granted Patent US 7,183,633
Granted Patent B2
US 7,183,633 · App. 10/469,516 · Granted Feb 27, 2007

Optical cross-connect system

Assignee: Analog Devices Inc.
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Quick Facts
Patent No.
US 7,183,633
App. No.
10/469,516
Granted
Feb 27, 2007
Kind
B2
Abstract

An optical cross-connect switch comprises a base ( 216 ), a flap ( 211 ) and one or more electrically conductive landing pads ( 222 ) connected to the flap ( 211 ). The flap ( 211 ) has a bottom portion that is movably coupled to the base ( 216 ) such that the flap ( 211 ) is movable with respect to a plane of the base ( 216 ) from a first orientation to a second orientation. The one or more landing pads ( 222 ) are electrically isolated from the flap ( 211 ) and electrically coupled to be equipotential with a landing surface.

Claims (27)

1. An optical cross-connect switch, comprising:

a base;

a flap having a bottom portion movably coupled to the base such that the flap is movable with respect to a plane of the base from a first orientation to a second orientation; and

one or more electrically conductive landing pads connected to the flap, wherein the one or more landing pads are electrically isolated from the flap and electrically coupled to be equipotential with a landing surface, wherein at least one landing pad is substantially parallel to the flap.

2. The switch of claim 1 , wherein the base further includes at least one cantilevered anti-stiction bar.

3. The switch of claim 1 or 2 , wherein a magnetic field is used to create a first actuation force to manipulate the flap.

4. The switch of claim 1 or 2 , wherein an acoustic pulse is used to create a first actuation force to manipulate the flap.

5. The switch of claim 1 or 2 , wherein a pneumatic pressure is used to create a first actuation force to manipulate the flap.

6. The switch of claim 1 , 2 , 3 , 4 or 5 further including a stop configured to contact a portion of the flap in a contact area sized so that, upon application of an electrostatic bias between the flap and the stop, a sufficient second force holds the flap against the stop.

7. The switch of claim 6 wherein stop is comprised of two vertical walls.

8. The switch of claim 6 or 7 wherein the stop includes a sidewall made of silicon and having crystalline orientation of <111>.

9. The switch of claim 1 , 2 , 3 , 4 , 5 , 6 , 7 or 8 further including a microcontroller electrically coupled to the flap to enable the flap to be grounded or held at a voltage potential.

10. The switch of claim 9 , wherein the microcontroller also controls the first actuation force.

11. The switch of claim 9 , further comprising a magnet assembly electrically coupled to the microcontroller and sized less than 0.5″ in width, said magnet assembly positioned to surround the switch and provide magnetic force along both a Z and an X axis, wherein the microcontroller also controls the magnet assembly and wherein the first actuation force is magnetic.

12. The switch of claim 9 , 10 or 11 wherein the microcontroller stores the state of the flap and capacitive sensing is used to confirm that the flap is in the correct state.

13. The switch of claim 9 , 10 , 11 further including a magnetoresistive element coupled to the flap, wherein the microcontroller stores the state of the flap and magnetoresistive sensing is used to confirm that the flap is in the correct state.

14. The switch of claim 13 further including a magnetoresistive element coupled to the base, wherein the microcontroller stores the state of the flap and magnetoresistive sensing is used to confirm that the flap is in the correct state.

15. The switch of claim 13 or 14 further including a magnetoresistive element coupled to the stop, wherein the microcontroller stores the state of the flap and magnetoresistive sensing is used to confirm that the flap is in the correct state.

16. The switch of claim 6 , 7 or 8 , further including a charge-storing circuit electrically coupled between the stop and an electrical ground, an isolator element electrically coupled between the clamping surface and a source of clamping voltage, wherein the isolator element is configured to electrically isolate the source of clamping voltage from the clamping surface in the event of a power failure.

17. The switch of claim 16 wherein the isolator element is an opto-isolator or a low leakage diode.

18. The switch of claim 16 or 17 , wherein the charge-storing circuit includes a capacitor.

19. The switchof claims 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 , 10 , 11 , 12 , 13 , 14 , 15 , 16 , 17 or 18 , further including an enclosure for sealing the flap and having one or more sidewalls, an optical element coupled to at least one of the sidewalls, wherein at least one of the one or more sidewalls or the optical element includes a surface that is angled with respect to an optical plane.

20. The switch of claim 18 , wherein the enclosure is evacuated.

21. The switch of claim 18 , wherein the enclosure is filled with a gas.

22. The switch of claim 9 , 10 , 11 , 12 , 13 , 14 or 15 wherein the microcontroller also monitors voltage levels and engage a signal transmission in the event of a power failure.

23. The switch of claim 16 , 17 , 18 , 19 or 20 further including a microcontroller to monitor voltage levels, whereby the microcontroller may engage a signal transmission in the event of a power failure.

24. The switch of claim 9 , 10 , 11 , 12 , 13 , 14 or 15 , further including a stop configured to contact a portion of the cantilever in a contact area sized so that, upon application of an electrostatic bias between the flap and the stop, a sufficient second force holds the flap against the stop; and a charge-storing circuit electrically coupled between the stop and an electrical ground, an isolator element electrically coupled between the clamping surface and a source of clamping voltage, wherein the isolator element is configured to electrically isolate the source of clamping voltage from the clamping surface in the event of a power failure.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2005
From: DANEMAN, MICHAEL J.; WALL, FRANKLIN; BEHIN, BEHRANG; CHAPARALA, MURAL; CHANG, MARK W.; KIANG, MENG-HSIUNG; LIN, CHUANG CHIA; BEERLING, TIMOTHY
To: ONIX MICROSYSTEMS
Reel/Frame 017103/0024 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 19, 2005
From: DALTON, SCOTT; PANYKO, STEPHEN; KOBRIN, BORIS; LAU, KAM YIN
To: ONIX MICROSYSTEMS
Reel/Frame 017103/0225 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 19, 2005
From: ONIX MICROSYSTEMS
To: ANALOG DEVICES, INC.
Reel/Frame 017104/0243 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 12, 2004
From: ONIX MICROSYSTEMS, INC.
To: ANALOG DEVICES, INC.
Reel/Frame 015552/0472 →
Priority Claims (2)
US 01/011046 · Apr 4, 2001 · national
US 01/011047 · Apr 4, 2001 · national
Continuity (13)
Continuation In Part 0998990500 · Nov 20, 2001
Continuation In Part 0999253100 · Nov 6, 2001
Continuation In Part 0999253000 · Nov 6, 2001
Continuation In Part 0994921000 · Sep 7, 2001
Continuation In Part 0990084100 · Jul 7, 2001
Continuation In Part 0989176000 · Jun 25, 2001
Continuation In Part 0985387000 · May 11, 2001
Continuation In Part 0985386800 · May 11, 2001
Continuation In Part 0985386900 · May 11, 2001
Continuation In Part 0985158700 · May 8, 2001
Continuation In Part 0979812900 · Mar 1, 2001
Provisional Application 6030375500 · Jul 7, 2001
Related Publication 20060049826A1 · Mar 9, 2006