Generation of metal holes by via mutation
View Patent ↗A reduction in the intersection of vias on the last layer (“VL”) and holes in the last thin metal layer (“MLHOLE”) can be achieved without degrading product yield or robustness or increasing copper dishing. The mutation of some dense redundant VLs to MLHOLEs decreases the number of intersections between VLs and MLHOLEs.
1. A method of designing a semiconductor interconnect architecture including a pair of metal layers interconnected by a plurality of conductive vias, the method comprising:
identifying the plurality of vias from a via array design;
using a spatial relationship between locations of the plurality of vias in the via array design and a location of one of the metal layers to identify in the one metal layer a predetermined position of a hole in said one metal layer relative to at least one via in the via array design;
requiring the hole in said one metal layer at said predetermined position; and
mutating the at least one via from tha plurality of vias into the hole in said one metal layer at said predetermined position.
2. The method of claim 1 , including assigning to at least one of the plurality of vias a cross-sectional area greater than a via cross-sectional area associated with the via array design.
3. The method of claim 1 , wherein said using step, said requiring step and said mutating step comprise renaming the at least one via as the hole.
4. The method of claim 3 , including assigning to the hole a cross-sectional area greater than a cross-sectional area of the at least one via.
5. The method of claim 4 , including assigning to at least one of the plurality of vias a cross-sectional area greater than a via cross-sectional area associated with the via array design.
6. The method of claim 1 , wherein said hole is in a relatively overlying relationship with a position occupied by the at least one via in the via array design.
7. The method of claim 1 , including assigning to the hole a cross-sectional area greater than a cross-sectional area of the at least one via.
8. The method of claim 1 , including assigning to the hole a cross-sectional area greater than a cross-sectional area of the at least one via.
9. The method of claim 1 , including assigning to at least one of the plurality of vias a cross-sectional area greater than a via cross-sectional area associated with the via array design.