Memory channel utilizing permuting status patterns

1. A memory agent comprising:

a pattern generator to generate a status pattern;

send logic to send a command;

wherein the pattern generator includes logic to permute the status pattern in a predictable manner and

wherein the memory agent includes the send logic to resend the command from the memory agent if a first pattern received from a second memory agent matches the status pattern.

2. A memory agent according to claim 1 wherein the pattern generator includes logic to generate the status pattern with a CRC error.

3. A memory agent according to claim 2 wherein the pattern generator includes logic to generate the status pattern without a CRC error if the memory agent is operating in a fail-over mode.

4. A memory agent according to claim 1 wherein the memory agent includes logic to interpret a status pattern with a CRC error as a status pattern.

5. A memory agent according to claim 4 wherein the memory agent includes logic to interpret a status pattern without a CRC error as a pattern other than a status pattern.

6. A memory agent according to claim 1 wherein the memory agent comprises a memory buffer.

7. A memory agent according to claim 1 wherein the memory agent comprises a memory module.

8. A memory agent according to claim 1 wherein the memory agent comprises a memory controller.

9. A memory agent according to claim 1 wherein the memory agent includes logic to interpret a second pattern received from the second memory agent as a status pattern if the second received pattern matches the pennuted status pattern.

10. A memory agent according to claim 1 wherein the memory agent includes logic to interpret a second received pattern from the second memory agent as a pattern other than a status pattern if the second received pattern does not match the permuted status pattern.

11. A memory agent according to claim 1 wherein the pattern generator comprises dedicated logic circuitry.

12. A memory agent according to claim 11 wherein the dedicated logic circuitry comprises a feedback shift register.

13. A memory agent according to claim 1 wherein the status pattern is an idle pattern.

14. A memory agent according to claim 1 wherein the status pattern is an alert pattern.

15. A memory agent according to claim 1 wherein the pattern generator generates a first type of the status pattern to be a complement of a second type of the status pattern.

16. A memory agent according to claim 15 wherein:

the first type of the status pattern is an idle pattern; and

the second type of the status pattern is an alert pattern.

17. A memory agent according to claim 1 where the pattern generator includes logic to permute the status pattern according to a predetermined sequence.

18. A memory agent according to claim 1 where the pattern generator includes logic to permute the status pattern each time a status pattern is sent or received.

19. A system comprising:

a first memory agent; and

a second memory agent coupled to the first memory agent through a link;

wherein the first memory agent includes logic to send data patterns and status patterns over the link;

wherein the second memory agent includes logic to receive the data patterns and status patterns over the link with one of the status patterns;

wherein the first memory agent includes logic to permute the status patterns in a predictable manner; and

wherein the second memory agent includes the send logic to resend the command if with one of the status patterns received from the first memory agent matches a status pattern generated by the second memory agent.

20. A system according to claim 19 wherein the second memory agent includes logic to interpret the permuted status patterns.

21. A system according to claim 20 wherein:

the first memory agent comprises a memory module; and

the second memory agent comprises a memory controller.

22. A system according to claim 20 wherein:

the first memory agent comprises a memory buffer; and

the second memory agent comprises a memory controller.

23. A system according to claim 19 wherein the second memory agent includes logic to interpret a second pattern received from the first memory agent as a status pattern if the second received pattern matches a permuted status pattern generated by the second memory agent.

24. A system according to claim 19 wherein the second memory agent includes logic to interpret a second pattern received from the first memory agent as a data pattern if the second received pattern does not match a permuted status pattern generated by the second memory agent.

25. A system according to claim 19 where the first memory agent includes logic to permute the status patterns according to a predetermined sequence.

26. A system according to claim 19 where first memory agent includes logic to permute the status patterns each time a status pattern is sent or received.

27. A method comprising:

sending data patterns from a memory agent over a link;

sending a command from the memory agent;

sending status patterns from the memory agent over the link;

permuting the status patterns; and

resending the command from the memory agent if a first pattern received from a second memory agent matches one of the status patterns.

28. A method according to claim 27 wherein one or more of the status patterns includes a CRC error.

29. A method according to claim 28 wherein the status patterns do not include a CRC error if the memory agent is operating in a fail-over mode.

30. A method according to claim 27 further comprising permuting the status patterns in a predictable manner.

31. A method according to claim 30 further comprising permuting the status patterns according to a predetermined sequence.

32. A method according to claim 30 further comprising permuting the status patterns each time a status pattern is sent or received.