Method and apparatus for trimming a phase detector in a delay-locked-loop
View Patent ↗Methods and apparatus are provided for trimming a phase detector in a delay-locked-loop. A latch that evaluates a phase offset between two signals is trimmed by applying two signals to the latch that are substantially phase aligned; obtaining a phase offset between the two signals measured by the latch; and adjusting a trim setting of one or more buffers associated with the two signals until the phase offset satisfies one or more predefined criteria. The two signals can be a clock signal and an inverted version of the clock signal. The two signals can be a source of phase aligned data generated from a single clock source.
1. A method for trimming a phase detector comprised of a latch and one or more pre-latch buffers, wherein said latch evaluates a phase offset between two signals, said method comprising the steps of:
applying two signals to said pre-latch buffets that are substantially phase aligned;
obtaining a phase offset attributable to said phase detector between said two signals measured by said latch; and
adjusting a trim setting of said one or more pre-latch buffers associated with said two signals until said phase offset satisfies one or more predefined criteria.
2. The method of claim 1 , wherein said latch is within a phase detector in a delay-locked loop.
3. The method of claim 1 , wherein said two signals are a clock signal and an inverted version of said clock signal.
4. The method of claim 1 , wherein said two signals are a source of phase aligned data generated from a single clock source.
5. The method of claim 4 , wherein said source of phase aligned data is obtained by aligning one or more edges of signals generated by delay elements that are 180 degrees out of phase.
6. The method of claim 5 , wherein said one or more edges comprise a rising edge or a falling edge.
7. The method of claim 4 , wherein said single clock source is a central interpolator in a clock and data recovery circuit.
8. The method of claim 1 , wherein said obtaining step further comprises the step of applying said two signals to said latch and determining if edges associated with each of said two signals ate substantially aligned.
9. A delay-locked loop circuit, comprising:
a phase detector comprising:
at least one latch for determining a phase offset attributable to said phase detector between two signals that are substantially phase aligned;
one or more pre-latch buffers associated with said two signals; and
a trim control terminal for adjusting a trim setting of said one or more pre-latch buffers associated with said two signals until said phase offset satisfies one or more predefined criteria.
10. The delay-locked loop circuit of claim 9 , wherein said two signals are a clock signal and an inverted version of said clock signal.
11. The delay-locked loop circuit of claim 9 , wherein said two signals are a source of phase aligned data generated from a single clock source.
12. The delay-locked loop circuit of claim 11 , wherein said source of phase aligned data is obtained by aligning one or more edges of signals generated by delay elements that are 180 degrees out of phase.
13. The delay-locked loop circuit of claim 12 , wherein said one or more edges comprise a rising edge or a falling edge.
14. The delay-locked loop circuit of claim 11 , wherein said single clock source is a central interpolator in a clock and data recovery circuit.
15. The delay-locked loop circuit of claim 9 , wherein said phase offset is determined by applying said two signals to said latch and determining if edges associated with each of said two signals are substantially aligned.
16. An integrated circuit, comprising:
a delay-locked loop, comprising:
a phase detector comprising:
at least one latch for determining a phase offset attributable to said phase detector between two signals that are substantially phase aligned;
one or more pre-latch buffers associated with said two signals; and
a trim control terminal for adjusting a trim setting of said one or more pre-latch buffers associated with said two signals until said phase offset satisfies one or more predefined criteria.
17. The integrated circuit of claim 16 , wherein said two signals are a clock signal and an inverted version of said clock signal.
18. The integrated circuit of claim 16 , wherein said two signals are a source of phase aligned data generated from a single clock source.
19. The integrated circuit of claim 18 , wherein said source of phase aligned data is obtained by aligning one or more edges of signals generated by delay elements that are 180 degrees out of phase.
20. The integrated circuit of claim 18 , wherein said single clock source is a central interpolator in a clock and data recovery circuit.