Memory system having multi-terminated multi-drop bus
Provided is a memory system having a multi-drop bus structure. The memory system includes a bus, a memory controller in which a port connected to the bus is terminated by a resistor having a first impedance value, a connector connected to a point having the first impedance value from the memory controller on a bus line, and a memory module connected to the connector. The memory module includes a first load connected to the connector and having the first impedance value, a second load connected to the first load and having a second impedance value, a first chip in which a port connected to the second load is terminated by a resistor having the second impedance value, a via hole penetrating a printed circuit board of the memory module between the first load and the second load, a third load connected to the via hole and having the second impedance value, and a second chip in which a port connected to the third load is terminated by a resistor having the second impedance value. The first load, the second load, and a first chip are formed on a first surface of the memory module while the third load and the second chip are formed on a second surface thereof.
1. A memory system having a multi-drop bus structure comprising:
a bus line;
a connector connected to a bus line;
a memory controller in which a port connected to the bus line is terminated by a resistor having a second impedance value; and
a memory module connected to the connector and having at least one memory chip and a termination resistor in the memory chip,
wherein the memory module comprises:
a first load connected to the connector;
a second load connected to the first load and having a first impedance value;
a first chip in which a port connected to the second load is terminated by a resistor having the first impedance value;
a via hole penetrating a printed circuit board of the memory module between the first load and the second load;
a third load connected to the via hole and having the first impedance value; and
a second chip in which a port connected to the second load is terminated by a resistor having the first impedance value,
wherein the first load, the second load, and the first chip are formed on a first surface of the memory module while the third load and the second chip are formed on a second surface thereof, and a property impedance of a wire to which the memory chip is connected has the first impedance value.
2. The memory system of claim 1 , wherein the second impedance value is twice the first impedance value.
3. The memory system of claim 2 , wherein the first load has an impedance value corresponding to half of the first impedance value.
4. A memory system having, a multi-drop bus structure comprising:
a bus line;
a memory controller in which a port connected to the bus is terminated by a resistor having a first impedance value;
a connector connected to a point having the first impedance value from the memory controller on a bus line; and
a memory module connected to the connector, the memory module comprising:
a first load connected to the connector and having the first impedance value;
a second load connected to the first load and having a second impedance value;
a first chip in which a port connected to the second load is terminated by a resistor having the second impedance value;
a via hole penetrating a printed circuit board of the memory module between the first load and the second load;
a third load connected to the via hole and having the second impedance value; and
a second chip in which a port connected to the third load is terminated by a resistor having the second impedance value,
wherein the first load, the second load, and the first chip are formed on a first surface of the memory module while the third load and the second chip are formed on a second surface thereof.
5. The memory system of claim 4 , wherein the second impedance value is twice the first impedance value.
6. A memory module comprises:
a first load connected to a memory module electrode and having a first impedance value;
a second load connected to the first load and having a second impedance value;
a first chip in which a port connected to the second load is terminated by a resistor having the second impedance value;
a via hole penetrating a printed circuit board of the memory module between the first load and the second load;
a third load connected to the via hole and having the second impedance value; and
a second chip in which a port connected to the third load is terminated by a resistor having the second impedance value,
wherein the first load, the second load, and the first chip are formed on a first surface of the memory module while the third load and the second chip are formed on a second surface thereof.
7. The memory module of claim 6 , wherein the second impedance value is twice the first impedance value.