Fast/slow state machine latch
View Patent ↗A fast/slow state machine latch is provided that generates fast and slow select signals for a single toggle, low power multiplexer circuit. In accordance with an embodiment of the present invention, the fast/slow state machine latch includes a first latch with a delayed output, a second latch with an undelayed output, an inverter for coupling the delayed output of the first latch to an input of the second latch, and an exclusive-OR (XOR) gate coupled to the delayed output of the first latch and a data input, an output of the XOR gate coupled to an input of the first latch. A method for incorporating low power multiplexer circuits into a circuit design with minimal input from a circuit designer is also provided.
1. A circuit design method, comprising:
selecting a candidate multiplexer circuit in a circuit design for replacement, wherein the candidate multiplexer circuit comprises a latch and a multiplexer;
swapping the multiplexer of the candidate multiplexer circuit with a single toggle, low power multiplexer circuit;
swapping the latch of the candidate multiplexer with a fast/slow state machine latch, wherein the fast/slow state machine latch provides a pair of select signals for driving a select line of the single toggle, low power multiplexer circuit; and
performing a timing check to ensure proper timing of the select signals.
2. The circuit design method of claim 1 , wherein the fast/slow state machine latch comprises:
a first latch providing a slow select signal;
a second latch providing a fast select signal;
an inverter for coupling the slow select signal of the first latch to an input of the second latch; and
an exclusive-OR (XOR) gate coupled to the slow select signal of the first latch and a data input, an output of the XOR gate coupled to an input of the first latch.
3. The circuit design method of claim 2 , wherein the step of providing a timing check further comprises:
delaying the slow select signal such that the slow select signal is timed to arrive at a select line of the single toggle, low power multiplexer after a slowest data arrives at the datain port of the single toggle, low power multiplexer circuit.
4. The circuit design method of claim 2 , wherein the fast select signal comprises an inverse of a previous slow select signal provided by the first latch.
5. The circuit design method of claim 2 , wherein the slow select signal comprises an exclusive-OR of the data input and a previous slow select signal provided by the first latch.
6. The circuit design method of claim 1 , wherein the step of selecting a candidate multiplexer circuit for replacement further comprises:
selecting a candidate multiplexer circuit having a higher power consumption than the single toggle, low power multiplexer circuit.